The present disclosure relates to transistor devices, and more specifically, to transistor devices that utilize a gate conductor that includes sections that are doped in different manners and to a diffusion barrier for use between such sections of the gate conductor.
Within a transistor, a semiconductor (or channel region) is positioned between a conductive “source” region and a similarly conductive “drain” region. When the semiconductor is in a conductive state, the semiconductor allows electrical current to flow between the source and drain. A “gate” is a conductive element that is electrically separated from the semiconductor by a “gate oxide” (which is an insulator) and current/voltage within the gate changes the conductivity of the channel region of the transistor.
In complementary metal oxide semiconductor (CMOS) devices, immediately adjacent transistors are “complementary” to one another, meaning that the adjacent transistors have opposite polarities (one is a positive-type (P-type) and the other is negative-type (N-type)). To increase manufacturing efficiency, a single polysilicon gate is formed over these complementary adjacent transistors, and different portions of the polysilicon gate are subjected to opposite doping regimes to allow each different transistor to have a gate conductor that has a doping polarity appropriate for the polarity of the underlying channel region.
However, the polysilicon gate is often pre-doped at a very high dose. This doping is done before gate etching and anneals associated with the source/drain diffusions. An issue has been observed in very tight ground rule layouts where the dopants diffuse into opposite polarity regions of the gate conductor. If N-type doping gets into the gate over the positive type transistor or P-type doping gets into the gate over the negative type transistor, large gate depletion can occur, which causes significant transistor performance issues.